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Abstract

A computer-aided synthesis and verification tool is provided for modeling a digital device at a behavioral level and for synthesizing to a structural level utilizing user-defined attributes. The behavioral level is represented as a Data Dependency Graph (DDG) having a plurality of operations (shown as nodes) and operands (shown as arcs) which connect the nodes. Each operation or node is represented as a graphical icon, wherein the icon can have user-defined attributes associated with it. The attributes, nodes, and arcs are compiled and reduced to a Register Transfer Level (RTL) simulation model compatible with present VHDL and Verilog formats. Conversion from a behavioral model to an RTL model includes monitoring the internal states at rising clock edges and constructing states, events and event transistions (i.e., control path information) for each data value in the matrix of values within the data path. The resulting RTL model therefore includes both control path information and data path information, and can be further reduced to technology dependent or silicon dependent circuits or structures.

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First Claim