Importance

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Abstract

A computer system includes first and second integrated circuits. A direct memory access (DMA) controller circuit on the first integrated circuit receives a direct memory access request (DRQ) input signal which is provided from the second integrated circuit, across a signal line of said bus. The value of the DRQ signal is updated at predetermined intervals on the signal line. A DMA synchronization control circuit on the first integrated circuit prevents the DMA controller circuit from evaluating its DRQ input signal, once a DMA operation has started, until after the value of the DRQ input signal has been updated by the second integrated circuit. In addition, the DMA acknowledge signal from the DMA controller circuit is mapped to an address indicative of the acknowledge signal, and the address is sent to the second integrated circuit. A decoder circuit on the second integrated circuit decodes the address and provides the appropriate DMA acknowledge signal to a functional block on the second integrated circuit according to the address received.

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First Claim