Processor for VLIW instruction

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6044450
SERIAL NO

08824486

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit. In this case, each instruction expanding circuit supplies after each small instruction NOP instructions same in number as that designated by a NOP number associated with each small instruction in this grouped instruction.

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Patent Owner(s)

  • HITACHI, LTD.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ito, Masanao Kokubunji, JP 8 119
Nagashima, Shigeo Hachioji, JP 42 1236
Shimada, Kentaro Hadano, JP 93 1386
Tamaki, Yoshiko Kodaira, JP 21 860
Tanaka, Yoshikazu Tokorozawa, JP 317 3906
Totsuka, Yonetaro Kokubunji, JP 23 513
Tsushima, Yuji Kokubunji, JP 78 1697

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