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Abstract

Clock-to-signal skew has largely been accepted and tolerated as a design issue; a memory controller that addresses the issue is described. The memory controller is configurable to operate either in a high-performance mode with external synchronization or in a normal mode. In high-performance mode, the memory controller generates a memory control signal, one clock cycle earlier than it would in normal mode, as input for a register. The register buffers the (early) signal. An external clock signal serves as a synchronization event; that is, the clock signal synchronizes the memory control signal by causing the register to output that signal at a more precisely controlled time than might otherwise occur using the memory controller alone. Thus, the use of the external clock signal helps compensate for the effects of clock-to-signal skew; multiple external synchronization registers may also be used.

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First Claim