Resin-encapsulated LOC semiconductor device having a thin inner lead
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United States of America Patent
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-
Apr 4, 2000
Grant Date -
N/A
app pub date -
Feb 17, 1998
filing date -
Feb 17, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor device of the present invention has an LOC (Lead On Chip) structure. An end portion of an inner lead made thinner than an outer lead by cutting its lower surface by a predetermined thickness and a bus bar thinned to have the same thickness as the end portion of the inner lead are bonded to the surface of a semiconductor chip on which circuits are formed, with a protective film and an insulating tape interposed therebetween. A bonding wire is bonded to the thin portion of the inner lead or the thin bus bar. The thickness from the upper surface of the semiconductor chip to the upper surface of the inner lead can be reduced by the cut portion. A thin package can be realized without deteriorating the reliability with the normal thickness of the outer lead, the insulating tape and an encapsulating resin and the normal loop height of the bonding wire.
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