Process of testing integrated circuit dies on a wafer
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United States of America Patent
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-
Apr 4, 2000
Grant Date -
N/A
app pub date -
Oct 31, 1996
filing date -
Oct 31, 1995
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A semiconductor wafer has integrated circuit dies formed in an array of rows and columns. Selector circuits occur in the areas between the dies and are electrically connected to the individual dies for selecting between a functional mode and a bypass mode for testing. Probe areas are formed on the periphery of the wafer for accepting probe pins without contacting the bond pads of the dies. The dies and selector circuits are electrically connected to the probe areas for conducting electrical testing of the dies. The testing occurs by selecting only one die in a particular row and column and maintaining the remaining dies in a standby mode.
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