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Abstract

A decision feedback equalizer circuit employing a current mode finite impulse response (FIR) filter. A decision feedback equalizer circuit comprises an attenuator block for scaling a received voltage signal, a first transconductor (voltage-to-current converter) for converting the received voltage signal to a current signal, a current mode finite impulse response (FIR) filter for adding or subtracting current increments from the current signal and generating an equalized current signal, a second transconductor (current-to-voltage converter) for converting the equalized current signal into an equalized voltage signal, a positive slicer block for determining when the equalized voltage signal achieves a positive threshold level, a negative slicer block for determining when the equalized voltage signal achieves a negative threshold level, and a plurality of delay lines coupled respectively to the slicer blocks and to the current mode FIR filter for providing tap enable signals to the current mode FIR filter in response to signals received from the slicers. The decision feedback equalizer circuit may further comprise a baseline wander correction block for providing a correction current to the current mode FIR filter to compensate for baseline wander in the input voltage signal, and an adaptation block for providing compensation signals to the current mode FIR filter to insure that the equalized voltage signal conforms to a predetermined format.

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