Semiconductor memory device with multiplied internal clock

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6047344
SERIAL NO

09034218

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

The practical operation speed of the memory device is increased by multiplexing input and output signals so as to increase the internal operation frequency higher than the external clock frequency. The feature of the memory device of the present invention is that it has the function of making the internal operation frequency higher than the external clock frequency by making the external bit width larger than the internal bit width, writing write data by dividing them successively by time division operation, into those having an internal bit width, and allocating read data to use an entire external bit width. According to the present invention, the practical operation speed of the memory device assembled on the board can be increased over the upper frequency limit of signals transmitted through the wiring on the board, and the high frequency performance of the memory device can be tested at the step of the die sorting test.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBATOKYO 105-0023

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kawasumi, Atsushi Yokohama, JP 90 803
Miyano, Shinji Yokohama, JP 51 1016

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation