Process of fabricating a semiconductor device having nitrogen-containing silicon layer and refractory metal layer

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United States of America Patent

PATENT NO 6048795
SERIAL NO

08840550

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Abstract

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A field effect transistor available for 1 giga-bit dynamic random access memory device has a two-layer gate structure consisting of a lower layer of nitrogen-containing silicon and an upper layer of refractory metal, and the nitrogen-containing silicon effectively prevents the gate oxide layer from alkaline metals diffused from the refractory metal.

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Patent Owner(s)

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GODO KAISHA IP BRIDGE 1TOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujieda, Shinji Tokyo, JP 6 57
Miura, Yoshinao Tokyo, JP 47 570
Numasawa, Youichiro Tokyo, JP 1 9

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