Embedded static random access memory for field programmable gate array
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United States of America Patent
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Apr 11, 2000
Issued Date -
N/A
app pub date -
Mar 16, 1998
filing date -
Mar 16, 1998
priority date (Note) -
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Abstract
A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector is provided such that when both read and write ports in the SRAM block access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block or the new data being written to the SRAM block.
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