Clock synchronous semiconductor memory device capable of preventing outputting of invalid data
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 11, 2000
Grant Date -
N/A
app pub date -
Jul 27, 1998
filing date -
Jan 23, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A gate circuit is turned on in synchronization with an internal clock signal at a timing faster than activation of an output buffer circuit, and internal data is transmitted from the gate circuit to an output buffer circuit externally outputting data. Generation of an internal clock signal is stopped at a timing faster than deactivation of the output buffer circuit, and the gate circuit is set to the latching state. According such arrangement, output of invalid data is prevented.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully