System and method for maintaining memory coherency in a computer system having multiple system buses
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United States of America Patent
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Apr 11, 2000
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N/A
app pub date -
Jan 12, 1999
filing date -
Sep 16, 1996
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Abstract
A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.
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