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Abstract

An apparatus and method which sequentially selects subsets of data bits read in parallel from an array of memory cells (each cell being operated as a multistate memory device) and sequentially asserts the selected subsets to a data bus. Preferably, the cells are flash memory cells. Preferably, the apparatus includes a sense amplifier circuit, a multiplexer, and circuitry operable to read a number (N) of the cells in parallel, whether the cells are operated as binary or multistate devices. The sense amplifier has N input lines and MN output lines, where M is the number of binary bits in a binary representation of the data read from each cell operated as a multistate device. The multiplexer has MN inputs (each connected to one of the output lines of the sense amplifier circuit), N outputs connected to a data bus having N-bit width, and is controllable to output selected N-bit subsets of the MN bits received at its MN inputs. Another aspect of the invention is a memory system including such a multiplexer and read/write circuitry operable in a mode in which it writes data to selected cells of the array (leaving each cell in an erased or programmed state) or reads a binary data bit from each of N selected cells, where the read/write circuitry is also operable in another mode in which it writes data to selected cells of the array (leaving each cell in an erased state or a selected one of two or more possible programmed states) or reads data (indicative of an ordered set of at least two binary data bits) from each of N selected cells.

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First Claim