Hierarchical dual bus architecture for use in an electronic switching system employing a distributed control architecture
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United States of America Patent
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Apr 18, 2000
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N/A
app pub date -
Nov 14, 1996
filing date -
Dec 28, 1995
priority date (Note) -
Expired
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Abstract
A bus architecture for use in a data communication system provides a communication path between processors and one or more external devices including (M+1) hierarchical processors. Each of the processors is categorized into one of N hierarchies with M and N being a positive integer larger than 1, respectively, and N is smaller than (M+1). The bus architecture includes a bus having N buses, each of the buses coupled to one or more processors of a hierarchy and (N-1) linking means, and each of the linking means for coupling a bus of a hierarchy to a bus of a next hierarchy.
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