US Patent No: 6,053,950

Number of patents in Portfolio can not be more than 2000

Layout method for a clock tree in a semiconductor device

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Abstract

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A clock signal distribution circuit has a clock tree configuration. In the layout of the clock tree, a standard clock tree is prepared having a route buffer, a plurality of intermediate stage buffer cells and a plurality of last stage buffer cells connected in a hierarchical configuration. All of the clock lines have an equal length. If there are no set of flip-flops ina target integrated circuit corresponding to a set of last stage buffer cells, the set of last stage buffer cells are removed as a whole provided there is not other last stage buffer cells connected to a flip-flop.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
NEC ELECTRONICS CORPORATIONKAWASAKI-SHI KANAGAWA196

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shinagawa, Naoko Tokyo, JP 1 30

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Cadence Design Systems, Inc. (1)
* 5,452,239 Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system 274 1993
 
VLSI TECHNOLOGY, INC. (1)
* 5,638,291 Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew 48 1994
 
GLOBALFOUNDRIES INC. (1)
* 5,799,170 Simplified buffer manipulation using standard repowering function 17 1996
 
UNISYS CORPORATION (1)
* 5,864,487 Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool 30 1996
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
Cadence Design Systems, Inc. (2)
* 6,751,786 Clock tree synthesis for a hierarchically partitioned IC layout 22 2002
* 2003/0208,736 Clock tree synthesis for a hierarchically partitioned IC layout 3 2002
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (2)
7,017,132 Methodology to optimize hierarchical clock skew by clock delay compensation 8 2003
* 2005/0102,643 Methodology to optimize hierarchical clock skew by clock delay compensation 2 2003
 
GLOBALFOUNDRIES INC. (1)
* 7,765,425 Incrementally adjustable skew and duty cycle correction for clock signals within a clock distribution network 6 2006
 
SAMSUNG ELECTRONICS CO., LTD. (1)
* 6,311,314 System and method for evaluating the loading of a clock driver 8 1999
 
SUN MICROSYSTEMS, INC. (1)
* 2003/0074,175 Simulation by parts method for grid-based clock distribution design 2 2001
 
ORACLE AMERICA, INC. (2)
* 6,941,532 Clock skew verification methodology for grid-based design 7 2001
* 2003/0074,642 Clock skew verification methodology for grid-based design 0 2001
 
SOCIONEXT INC. (3)
* 6,487,707 LAYOUT DESIGN SYSTEM OF SEMICONDUCTOR IC DEVICE, LAYOUT DESIGN METHOD OF SEMICONDUCTOR IC DEVICE AND COMPUTER-READABLE RECORDING MEDIUM ON WHICH PROGRAMS FOR ALLOWING COMPUTER TO EXECUTE RESPECTIVE MEANS IN THE SYSTEM OR RESPECTIVE STEPS IN THE METHOD ARE RECORDED 6 2000
* 6,564,353 Method and apparatus for designing a clock distributing circuit, and computer readable storage medium storing a design program 6 2001
* 7,181,709 Clock delay adjusting method of semiconductor integrated circuit device and semiconductor integrated circuit device formed by the method 2 2004
 
CALLAHAN CELLULAR L.L.C. (2)
* 6,954,917 Function block architecture for gate array and method for forming an asic 9 2003
* 2003/0214,324 Function block architecture for gate array 1 2003
 
MENTOR GRAPHICS CORPORATION (15)
* 7,013,442 Synthesis strategies based on the appropriate use of inductance effects 18 2002
7,496,871 Mutual inductance extraction using dipole approximations 12 2004
7,426,706 Synthesis strategies based on the appropriate use of inductance effects 13 2006
* 2006/0143,586 Synthesis strategies based on the appropriate use of inductance effects 8 2006
8,161,438 Determining mutual inductance between intentional inductors 6 2006
* 2006/0282,492 Determining mutual inductance between intentional inductors 12 2006
8,091,054 Synthesis strategies based on the appropriate use of inductance effects 3 2008
8,549,449 Mutual inductance extraction using dipole approximations 5 2009
* 2009/0172,613 Mutual Inductance extraction using dipole approximations 10 2009
8,214,788 High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate 0 2009
8,650,522 Determining mutual inductance between intentional inductors 0 2012
8,732,648 High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate 7 2012
8,826,204 Mutual inductance extraction using dipole approximations 0 2013
8,910,108 High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate 0 2014
9,230,054 High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate 0 2014
 
RENESAS ELECTRONICS CORPORATION (4)
* 6,557,152 Method of designing signal distribution circuit and system for supporting the same 2 2000
* 6,542,005 Semiconductor integrated circuit and method of designing the same 4 2001
* 9,141,739 LSI design method 0 2013
* 2013/0219,352 LSI DESIGN METHOD 4 2013
 
KABUSHIKI KAISHA TOSHIBA (4)
* 2004/0237,060 Integrated circuit device, clock layout system, clock layout method, and clock layout program 5 2004
* 7,310,007 Logic circuit, system for reducing a clock skew, and method for reducing a clock skew 0 2005
* 2006/0055,423 Logic circuit, system for reducing a clock skew, and method for reducing a clock skew 0 2005
7,495,476 Logic circuit, system for reducing a clock skew, and method for reducing a clock skew 0 2007
 
NEC ELECTRONICS CORPORATION (2)
* 6,530,030 Apparatus for and a method of clock tree synthesis allocation wiring 1 2000
* 6,412,099 Apparatus and method for converting logical connection information of circuit 5 2000
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (2)
* 7,409,657 Clock tree layout method for semiconductor integrated circuit 2 2005
* 2007/0079,262 Clock tree layout method for semiconductor integrated circuit 0 2005
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (1)
* 6,725,389 Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit 2 2000
* Cited By Examiner