A clock signal distribution circuit has a clock tree configuration. In the layout of the clock tree, a standard clock tree is prepared having a route buffer, a plurality of intermediate stage buffer cells and a plurality of last stage buffer cells connected in a hierarchical configuration. All of the clock lines have an equal length. If there are no set of flip-flops ina target integrated circuit corresponding to a set of last stage buffer cells, the set of last stage buffer cells are removed as a whole provided there is not other last stage buffer cells connected to a flip-flop.
* 6,487,707 LAYOUT DESIGN SYSTEM OF SEMICONDUCTOR IC DEVICE, LAYOUT DESIGN METHOD OF SEMICONDUCTOR IC DEVICE AND COMPUTER-READABLE RECORDING MEDIUM ON WHICH PROGRAMS FOR ALLOWING COMPUTER TO EXECUTE RESPECTIVE MEANS IN THE SYSTEM OR RESPECTIVE STEPS IN THE METHOD ARE RECORDED
* 6,564,353 Method and apparatus for designing a clock distributing circuit, and computer readable storage medium storing a design program
* 7,181,709 Clock delay adjusting method of semiconductor integrated circuit device and semiconductor integrated circuit device formed by the method
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