US Patent No: 6,053,950

Number of patents in Portfolio can not be more than 2000

Layout method for a clock tree in a semiconductor device

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Abstract

A clock signal distribution circuit has a clock tree configuration. In the layout of the clock tree, a standard clock tree is prepared having a route buffer, a plurality of intermediate stage buffer cells and a plurality of last stage buffer cells connected in a hierarchical configuration. All of the clock lines have an equal length. If there are no set of flip-flops ina target integrated circuit corresponding to a set of last stage buffer cells, the set of last stage buffer cells are removed as a whole provided there is not other last stage buffer cells connected to a flip-flop.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
NEC ELECTRONICS CORPORATIONKAWASAKI-SHI KANAGAWA3284

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shinagawa, Naoko Tokyo, JP 1 23

Cited Art

Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (1)
5,452,239 Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system 235 1993
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5,799,170 Simplified buffer manipulation using standard repowering function 17 1996
 
UNISYS CORPORATION (1)
5,864,487 Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool 29 1996
 
VLSI TECHNOLOGY, INC. (1)
5,638,291 Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew 45 1994

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MENTOR GRAPHICS CORPORATION (6)
7,013,442 Synthesis strategies based on the appropriate use of inductance effects 10 2002
7,496,871 Mutual inductance extraction using dipole approximations 3 2004
7,426,706 Synthesis strategies based on the appropriate use of inductance effects 6 2006
8,161,438 Determining mutual inductance between intentional inductors 0 2006
8,091,054 Synthesis strategies based on the appropriate use of inductance effects 1 2008
8,214,788 High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate 2009
 
FUJITSU SEMICONDUCTOR LIMITED (2)
6,487,707 LAYOUT DESIGN SYSTEM OF SEMICONDUCTOR IC DEVICE, LAYOUT DESIGN METHOD OF SEMICONDUCTOR IC DEVICE AND COMPUTER-READABLE RECORDING MEDIUM ON WHICH PROGRAMS FOR ALLOWING COMPUTER TO EXECUTE RESPECTIVE MEANS IN THE SYSTEM OR RESPECTIVE STEPS IN THE METHOD ARE RECORDED 6 2000
6,564,353 Method and apparatus for designing a clock distributing circuit, and computer readable storage medium storing a design program 5 2001
 
KABUSHIKI KAISHA TOSHIBA (2)
7,310,007 Logic circuit, system for reducing a clock skew, and method for reducing a clock skew 0 2005
7,495,476 Logic circuit, system for reducing a clock skew, and method for reducing a clock skew 0 2007
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (2)
7,181,709 Clock delay adjusting method of semiconductor integrated circuit device and semiconductor integrated circuit device formed by the method 1 2004
7,409,657 Clock tree layout method for semiconductor integrated circuit 0 2005
 
NEC ELECTRONICS CORPORATION (2)
6,530,030 Apparatus for and a method of clock tree synthesis allocation wiring 0 2000
6,412,099 Apparatus and method for converting logical connection information of circuit 3 2000
 
RENESAS ELECTRONICS CORPORATION (2)
6,557,152 Method of designing signal distribution circuit and system for supporting the same 1 2000
6,542,005 Semiconductor integrated circuit and method of designing the same 3 2001
 
CADENCE DESIGN SYSTEMS, INC. (1)
6,751,786 Clock tree synthesis for a hierarchically partitioned IC layout 12 2002
 
GLOBALFOUNDRIES INC. (1)
7,765,425 Incrementally adjustable skew and duty cycle correction for clock signals within a clock distribution network 0 2006
 
LSI LOGIC CORPORATION (1)
6,725,389 Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit 2 2000
 
OTRSOTECH, LLC (1)
6,954,917 Function block architecture for gate array and method for forming an asic 3 2003
 
SAMSUNG ELECTRONICS CO., LTD. (1)
6,311,314 System and method for evaluating the loading of a clock driver 8 1999
 
SUN MICROSYSTEMS, INC. (1)
6,941,532 Clock skew verification methodology for grid-based design 5 2001
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
7,017,132 Methodology to optimize hierarchical clock skew by clock delay compensation 6 2003