Importance

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Abstract

A wide dynamic range bilinear multiplier implemented with an improved Gilbert cell mixer topology linearizies the top quad core of transistors Q1, Q2, Q3 and Q4 to provide a true bilinear multiplier whose output is linearly related to both inputs over a relatively substantial input power range without the need for an additional diode predistortion circuit or increased voltage. In order to improve the linearity of the upper quad core of transistors Q1, Q2, Q3 and Q4, these transistors Q1, Q2, Q3 and Q4 are implemented as either multi-tanh doublets or multi-tanh triplets. Each multi-tanh doublet includes two pair of common emitter configured transistors Q.sub.xe and Q.sub.xae. The linear input voltage range of the multi-tanh doublets is maximized by proper selection of the emitter areas Q.sub.xae relative to Q.sub.xe, where Ae is an area factor greater than 1. Each of the multi-tanh doublets is connected to the mirror current driver, formed from a pair of common emitter connected transistors, which act as current sinks for each of the multi-tanh doublets. In alternate embodiment of the invention, the upper transistor quad core transistors, Q1, Q2, Q3 and Q4 are formed from two multi-tanh triplets. An additional transistor is added to each of the multi-tanh doublets to form the multi-tanh triplets. In addition, another transistor is added to each of the mirror current driver circuits for each of the multi-tanh triplets. The use of the multi-tanh doublets and multi-tanh triplets allow the linear range of the upper quad transistor core transistors Q1, Q2, Q3 and Q4 to extended without the use of additional diode predistortion circuits or other performance penalties.

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First Claim