Architecture for a dual segment dual speed repeater
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United States of America Patent
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Apr 25, 2000
Grant Date -
N/A
app pub date -
Nov 13, 1997
filing date -
Nov 13, 1997
priority date (Note) -
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Abstract
The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.
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