Importance

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Abstract

A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for performing word length reads and writes to an external memory module containing a plurality of integrated circuit (IC) memory chips. The interface circuit contains a respective multiplexer and a respective register circuit for each byte of the word length data. The multiplexers select a byte of data from either an on-chip data bus or from a bus carrying data read from the external memory module. To perform a full length word write, the data from the on-chip bus is loaded into the registers (via the multiplexers) and then written to the memory module. To perform a partial length word write, a pre-read operation is performed at the target address and a word length data is loaded into the registers. The new data is then received over the on-chip data bus and routed by the multiplexers into the byte locations to be changed. The properly merged data is then written as a full length word to the memory module. To perform a full length word read, a word of data is loaded into the byte registers and then forwarded over the on-chip data bus. By the provision of a pre-read operation, all of the IC memory chips can share the same chip enable, output enable and write enable control signals thereby reducing pin count on the integrated circuit that contains the interface circuit.

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First Claim