Method of making a field effect transistor having an elevated source and an elevated drain

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6057200
SERIAL NO

08831360

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC390 MARCH ROAD SUITE 100 OTTAWA K2K 0G7

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Pan, Pai-Hung Boise, ID 96 2066
Prall, Kirk Boise, ID 104 1257
Sharan, Sujit Boise, ID 229 3419

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation