Programmable logic device incorporating a memory efficient interconnection device
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United States of America Patent
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May 2, 2000
Grant Date -
N/A
app pub date -
Jan 30, 1998
filing date -
Jun 20, 1997
priority date (Note) -
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Abstract
The invention relates to an integrated circuit that incorporates a memory efficient interconnection device. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). By using the memory efficient interconnection device, the invention is able to reduce the quantity of memory resources required to program the interconnection device while at the same time not substantially sacrificing the probability of fitting logic functions in the CPLD. The reduction in memory resources that the CPLD must provide leads to increased availability of precious die area for other components of the CPLD.
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