Importance

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Abstract

A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ('AGP') bus and host and memory buses, or as an interface bridge between a Fibre Channel Arbitrated Loop ('FC-AL') interface and the host and memory buses. The function of the multiple use chipset is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an FC-AL bridge interface is to be implemented. Selection of the type of bus bridge (AGP or FC-AL bridge interface) in the multiple use core logic chipset may be made by a hardware signal input, or by software during computer system configuration or power on self test ('POST'). Software configuration may also be determined upon detection of either an AGP or a FC-AL bridge interface device connected to the common AGP/ FC-AL bus. FC-AL information may be stored in the computer system main memory using the high speed FC-AL bridge interface.

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First Claim