Circuits, systems and method for address mapping
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United States of America Patent
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May 2, 2000
Issued Date -
N/A
app pub date -
Jul 9, 1996
filing date -
Sep 27, 1995
priority date (Note) -
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Abstract
An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.
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