Method of customizing integrated circuits by selective secondary deposition of interconnect material
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United States of America Patent
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May 9, 2000
Issued Date -
N/A
app pub date -
Apr 25, 1997
filing date -
Mar 24, 1997
priority date (Note) -
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Abstract
A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with a standard precision mask to define all possible connections, vias or cut-points, and 2) using a targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods. In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.
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