CMOS preferred state power-up latch
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United States of America Patent
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May 9, 2000
Grant Date -
N/A
app pub date -
Dec 4, 1998
filing date -
Dec 4, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A preferred state power-up latch circuit includes first and second cross-coupled P-channel transistors coupled to a first source of supply voltage, first and second cross-coupled N-channel transistors coupled to a second source of supply voltage, the transistors being coupled together to form a latch having an output node, in which at least one of the gate lengths is unequal to the other gates lengths in order to establish a preferred state upon power-up, and the gate width of all the transistors is equal.
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