CMOS output stage for providing stable quiescent current
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United States of America Patent
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May 9, 2000
Grant Date -
N/A
app pub date -
Apr 14, 1998
filing date -
Apr 28, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A CMOS output stage for providing stable quiescent current. The output stage includes a circuit that relates the quiescent current to the channel geometry of a power NMOS transistor and of an NMOS reference transistor of a reference current source. This configuration removes the dependency of the quiescent current on a power PMOS transistor used in the CMOS output stage, the threshold voltage of which may drift over time under high current and voltage operation, and adversely affects quiescent current stability.
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