Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions
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United States of America Patent
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May 9, 2000
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N/A
app pub date -
Jan 26, 1998
filing date -
Jan 26, 1998
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Abstract
Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.
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