Digital signal processor having data alignment buffer for performing unaligned data accesses
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United States of America Patent
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May 9, 2000
Grant Date -
N/A
app pub date -
Jan 16, 1998
filing date -
Jan 16, 1998
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Abstract
A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory may include first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and may include first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. A data alignment buffer is provided between the memory banks and the computation blocks. The data alignment buffer permits unaligned accesses to specified operands that are stored in different memory rows. The specified operands are supplied to one or both of the computation blocks in the same processor cycle.
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