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Abstract

Disclosed are a phase detector for detecting the phase difference between a data signal and a clock signal, and a timing extracting circuit for controlling the phase of the clock signal so that the phase relationship between the clock signal and the data signal is optimal by using the phase detector. The phase detector includes an edge detector for generating an edge signal at the rising edge and the falling edge of the data signal, and a D flip flop (D-FF) for storing and outputting the logical value of the clock signal at the time of generation of the edge signal, and holding the logical value until the generation of the next edge signal, thereby outputting a signal corresponding to the phase difference between the data signal and the clock signal. A clock generator in the timing extracting circuit having a PLL structure controls the phase of the clock signal so that the difference becomes optimal.

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First Claim