Memory system

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United States of America Patent

PATENT NO 6064591
SERIAL NO

09168989

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A memory system according to the present invention includes a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3, for example, 4) data, wherein the memory cell is operated as an n-level data storing memory cell when the number of times of write-erase sequence is smaller than a predetermined number of times, and the memory cell is operated as an m-level (m is an integer smaller than n, for example, 3) data storing memory cell when the number of times of write-erase sequence has exceeded the predetermined number of times. The number of information items (values) which can be stored in one memory cell is decreased with respect to a predetermined number of times of write-erase sequence. Thus, a memory system including a multi-level data storing memory cell and exhibiting improved durability against write-erase sequence operations is provided.

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Patent Owner(s)

  • KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Takeuchi, Ken Tokyo, JP 169 6391
Tanaka, Tomoharu Yokohama, JP 338 14532

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