Method of programming a multilevel nonvolatile memory cell with reduced number of erase operations
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United States of America Patent
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May 16, 2000
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N/A
app pub date -
Oct 3, 1997
filing date -
Oct 3, 1996
priority date (Note) -
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Abstract
In order to reduce the number of erase operations of a nonvolatile memory cell which stores a threshold voltage selected from among a plurality of threshold levels, a plurality of programming operations are implemented before an erase operation. That is, the programming operations are executed which respectively vary the threshold voltage of the memory cell to a different one of the plurality of threshold levels, or retain the previously stored threshold voltage of the memory cell. Thereafter, the memory cell is erased so as to return the voltage which is stored in the memory cell to a predetermined level, in response to all of the threshold levels having been used in the programming operations.
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