High-performance pass-gate isolation circuitry
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United States of America Patent
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May 16, 2000
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N/A
app pub date -
Sep 21, 1999
filing date -
May 27, 1998
priority date (Note) -
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Abstract
A pass gate isolation circuit (140) provides voltages to isolation pass gates (120) to allow higher speed access of rows in the memory array (105). When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage level at its output (315). The output becomes a steady state high voltage determined by a high voltage keeper circuit (320) and a voltage clamp circuit (325). When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and isolation of the row decoders (140).
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