Information processing system having a CPU for controlling access timings of separate memory and I/O buses
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
May 16, 2000
Issued Date -
N/A
app pub date -
May 27, 1998
filing date -
Oct 1, 1992
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In an information processing system, a wait state signal is inserted into a RDY signal, according to which data are transmitted through memory and I/O buses. A CPU controls the number of the wait state signal to adjust the difference of the transfer speeds of the memory and I/O buses. An MCU (Memory Controller Unit) includes configuration and refresh timer registers for specifying the configuration and the refresh cycle of a memory to be accessed.
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