Optimized computation of first and second divider values for a phase locked loop system

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United States of America Patent

PATENT NO 6065140
SERIAL NO

08846694

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Abstract

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Given a target frequency (F.sub.VE), a reference frequency (F.sub.R), an error limit (E.sub.L), and a first divider range (150), a first (R) and a second (N) integer divider value are computed. First, an initial first divider (R) is selected (152). Then, a second divider (N) is computed as equal to the target frequency (F.sub.VE) divided by the reference frequency (F.sub.R) multiplied times the selected first divider (154). Then an error term (E) is computed to quantify the error introduced by using integers as dividers (156). The divider terms are accepted (166) if the error term is less than the error limit (158). Otherwise, a new first integer divider (R) is selected (160), repeating the computation of the second (N) divider (154), the computation of the error (E) term (156), and the test of the error term (E) against a limit as a loop (158). This loop is repeated until either the error term (E) is less than the error (E.sub.L) limit (158), or the selected first divider term (R) is outside its specified range (162).

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Patent Owner(s)

Patent OwnerAddress
FREESCALE SEMICONDUCTOR INC6501 WILLIAM CANNON DRIVE WEST AUSTIN TX 78735

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Irwin, James Stuart Paige, TX 2 32

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