Static semiconductor memory device operating at high speed under lower power supply voltage
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United States of America Patent
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May 23, 2000
Grant Date -
N/A
app pub date -
May 5, 1998
filing date -
Apr 1, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A bit line load element for reducing a bit line amplitude during data reading is formed of p- and n-channel MOS transistors connected in parallel. When a word line is driven to the selected state, the p-channel MOS transistor is held off. In the data write operation, both the n- and p-channel MOS transistors are turned off. Even under a low power supply voltage, a sufficiently large bit line amplitude can be produced without an influence by a size of the bit line load element. By deactivating the bit line load element in the data write operation, it is possible to prevent generation of a DC current during data writing.
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