US Patent No: 6,067,262

Number of patents in Portfolio can not be more than 2000

Redundancy analysis for embedded memories with built-in self test and built-in self repair

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Abstract

An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self-test (BIST) circuitry and built-in-self-repair (BISR) circuitry. A BIST run is then performed on a predetermined portion of the integrated circuit to detect a set of faulty memory locations. The results of this first BIST run are stored. A second condition is applied to the die and a second BIST run is executed to generate a second set of faulty memory locations. The results of the second BIST run are stored and compared with the first result. If the results differ, the integrated circuit is rejected. Thus, a methodology for screening out field errors at the factory is disclosed using BIST/BISR circuitry.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
LSI LOGIC CORPORATIONMILPITAS, CA4131

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Irrinki, V Swamy Milpitas, CA 20 762
Phan, Tuan L San Jose, CA 5 384
Schwarz, William D San Jose, CA 4 290

Cited Art

Patent Info (Count) # Cites Year
 
LSI LOGIC CORPORATION (11)
5,068,547 Process monitor circuit 45 1990
5,249,281 Testable RAM architecture in a microprocessor having embedded cache memory 28 1990
5,524,114 Method and apparatus for testing semiconductor devices at speed 66 1993
5,486,786 Process monitor for CMOS integrated circuits 28 1994
5,577,050 Method and apparatus for configurable build-in self-repairing of ASIC memories design 101 1994
5,574,692 Memory testing apparatus for microelectronic integrated circuit 13 1995
5,663,967 Defect isolation using scan-path testing and electron beam probing in multi-level high density asics 51 1995
5,764,878 Built-in self repair system for embedded memories 62 1996
5,734,615 Memory testing apparatus for microelectronic integrated circuit 7 1996
5,956,350 Built in self repair for DRAMs using on-chip temperature sensing and heating 29 1997
5,909,404 Refresh sampling built-in self test and repair circuit 38 1998
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (4)
5,375,091 Method and apparatus for memory dynamic burn-in and test 17 1993
5,533,194 Hardware-assisted high speed memory test apparatus and method 24 1994
5,535,164 BIST tester for multiple memories 90 1995
5,631,868 Method and apparatus for testing redundant word and bit lines in a memory array 34 1995
 
ADVANCED WARMING SYSTEMS, INC. (1)
5,381,417 Circuit testing system 27 1993
 
ADVANTEST CORPORATION (1)
5,646,948 Apparatus for concurrently testing a plurality of semiconductor memories in parallel 41 1994
 
FREESCALE SEMICONDUCTOR, INC. (1)
5,761,489 Method and apparatus for scan testing with extended test vector storage in a multi-purpose memory system 32 1995
 
GLOBALFOUNDRIES INC. (1)
5,920,515 Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device 69 1997
 
MEDIATEK INC. (1)
5,497,381 Bitstream defect analysis method for integrated circuits 103 1995
 
NEC CORPORATION (1)
5,633,599 Semiconductor integrated circuit with a test circuit for input buffer threshold 11 1995
 
QIMONDA AG (1)
5,608,257 Fuse element for effective laser blow in an integrated circuit device 46 1995
 
SAMSUNG ELECTRONICS CO., LTD. (1)
5,748,543 Self repairing integrated circuit memory devices and methods 39 1996
 
SOLAR TURBINES INCORPORATED (1)
5,822,228 Method for using built in self test to characterize input-to-output delay time of embedded cores and other integrated circuits 26 1997
 
XILINX, INC. (1)
5,155,432 System for scan testing of logic circuit networks 49 1991
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
H1741 Method and apparatus for pattern sensitivity stress testing of memory systems 12 1994

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (74)
7,133,972 Memory hub with internal cache and/or memory access prediction 86 2002
7,149,874 Memory hub bypass circuit and method 9 2002
6,754,117 System and method for self-testing and repair of memory modules 124 2002
6,820,181 Method and system for controlling memory accesses to memory modules having a memory hub architecture 128 2002
7,245,145 Memory module and method having improved signal routing topology 10 2003
7,120,727 Reconfigurable memory module and method 113 2003
7,428,644 System and method for selective memory module power management 44 2003
7,260,685 Memory hub and access method having internal prefetch buffers 31 2003
7,107,415 Posted write buffers and methods of posting write requests in memory modules 21 2003
7,389,364 Apparatus and method for direct memory access in a hub-based memory system 2 2003
7,210,059 System and method for on-board diagnostics of memory modules 67 2003
7,133,991 Method and system for capturing and bypassing memory transactions in a hub-based memory system 11 2003
7,136,958 Multiple processor system and method including multiple memory hub modules 31 2003
7,310,752 System and method for on-board timing margin testing of memory modules 5 2003
7,194,593 Memory hub with integrated non-volatile memory 36 2003
7,120,743 Arbitration system and method for memory responses in a hub-based memory system 47 2003
7,216,196 Memory hub and method for memory system performance monitoring 62 2003
7,181,584 Dynamic command and/or address mirroring system and method for memory modules 36 2004
7,120,723 System and method for memory hub-based expansion bus 23 2004
7,213,082 Memory hub and method for providing memory sequencing hints 17 2004
6,980,042 Delay line synchronizer apparatus and method 45 2004
7,162,567 Memory hub and method for memory sequencing 33 2004
7,180,522 Apparatus and method for distributed memory control in a graphics processing system 5 2004
7,242,213 Memory module and method having improved signal routing topology 9 2004
7,249,236 Method and system for controlling memory accesses to memory modules having a memory hub architecture 3 2004
7,047,351 Memory hub bypass circuit and method 42 2005
7,222,197 Apparatus and method for direct memory access in a hub-based memory system 3 2005
7,282,947 Memory module and method having improved signal routing topology 8 2005
7,605,631 Delay line synchronizer apparatus and method 4 2005
7,415,567 Memory hub bypass circuit and method 2 2006
7,222,210 System and method for memory hub-based expansion bus 6 2006
7,206,887 System and method for memory hub-based expansion bus 38 2006
7,174,409 System and method for memory hub-based expansion bus 7 2006
7,418,526 Memory hub and method for providing memory sequencing hints 25 2006
7,490,211 Memory hub with integrated non-volatile memory 0 2006
7,251,714 Method and system for capturing and bypassing memory transactions in a hub-based memory system 6 2006
7,689,879 System and method for on-board timing margin testing of memory modules 4 2006
7,529,896 Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules 1 2006
7,437,579 System and method for selective memory module power management 37 2006
7,278,060 System and method for on-board diagnostics of memory modules 2 2006
7,412,566 Memory hub and access method having internal prefetch buffers 14 2006
7,386,649 Multiple processor system and method including multiple memory hub modules 15 2006
7,353,320 Memory hub and method for memory sequencing 2 2006
7,644,253 Memory hub with internal cache and/or memory access prediction 1 2006
7,546,435 Dynamic command and/or address mirroring system and method for memory modules 0 2007
7,370,134 System and method for memory hub-based expansion bus 23 2007
7,360,011 Memory hub and method for memory system performance monitoring 2 2007
7,716,444 Method and system for controlling memory accesses to memory modules having a memory hub architecture 3 2007
7,516,363 System and method for on-board diagnostics of memory modules 4 2007
7,557,601 Memory module and method having improved signal routing topology 2 2007
7,581,055 Multiple processor system and method including multiple memory hub modules 3 2007
7,818,712 Reconfigurable memory module and method 0 2008
7,562,178 Memory hub and method for memory sequencing 1 2008
7,533,213 Memory hub and method for memory system performance monitoring 1 2008
7,610,430 System and method for memory hub-based expansion bus 9 2008
7,966,430 Apparatus and method for direct memory access in a hub-based memory system 0 2008
8,127,081 Memory hub and access method having internal prefetch buffers 0 2008
7,913,122 System and method for on-board diagnostics of memory modules 0 2008
7,945,737 Memory hub with internal cache and/or memory access prediction 0 2009
7,975,122 Memory hub with integrated non-volatile memory 0 2009
7,746,095 Memory module and method having improved signal routing topology 2 2009
7,873,775 Multiple processor system and method including multiple memory hub modules 0 2009
8,164,375 Delay line synchronizer apparatus and method 0 2009
7,899,969 System and method for memory hub-based expansion bus 0 2009
7,958,412 System and method for on-board timing margin testing of memory modules 3 2010
7,908,452 Method and system for controlling memory accesses to memory modules having a memory hub architecture 0 2010
7,966,444 Reconfigurable memory module and method 0 2010
8,244,952 Multiple processor system and method including multiple memory hub modules 0 2011
8,086,815 System for controlling memory accesses to memory modules having a memory hub architecture 1 2011
8,195,918 Memory hub with internal cache and/or memory access prediction 0 2011
8,209,445 Apparatus and method for direct memory access in a hub-based memory system 0 2011
8,200,884 Reconfigurable memory module and method 2 2011
8,117,371 System and method for memory hub-based expansion bus 0 2011
8,234,479 System for controlling memory accesses to memory modules having a memory hub architecture 0 2011
 
MICRON TECHNOLOGY, INC. (52)
7,200,024 System and method for optically interconnecting memory devices 22 2002
7,254,331 System and method for multiple bit optical data transmission in memory systems 10 2002
6,944,743 Memory hub bypass circuit and method 0 2002
7,836,252 System and method for optimizing interconnections of memory devices in a multichip module 1 2002
7,102,907 Wavelength division multiplexed memory module, memory system and method 33 2002
6,937,057 Memory module and method having improved signal routing topology 0 2003
7,366,920 System and method for selective memory module power management 0 2003
7,234,070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 13 2003
7,137,024 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 0 2003
7,330,992 System and method for read synchronization of memory modules 4 2003
7,188,219 Buffer control system and method for a memory system having outstanding read and write request buffers 34 2004
7,788,451 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 10 2004
7,412,574 System and method for arbitration of memory responses in a hub-based memory system 14 2004
7,366,864 Memory hub architecture having programmable lane widths 1 2004
7,257,683 Memory arbitration system and method having an arbitration packet protocol 7 2004
7,447,240 Method and system for synchronizing communications links in a hub-based memory system 3 2004
7,590,797 System and method for optimizing interconnections of components in a multichip memory module 1 2004
7,222,213 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 31 2004
7,363,419 Method and system for terminating write commands in a hub-based memory system 30 2004
7,519,788 System and method for an asynchronous data buffer having buffer write and read pointers 4 2004
7,310,748 Memory hub tester interface and method for use thereof 9 2004
7,106,611 Wavelength division multiplexed memory module, memory system and method 20 2004
7,392,331 System and method for transmitting data packets in a computer system having a memory hub architecture 7 2004
7,289,347 System and method for optically interconnecting memory devices 7 2005
7,272,682 Memory hub bypass circuit and method 0 2006
7,870,329 System and method for optimizing interconnections of components in a multichip memory module 2 2006
7,594,088 System and method for an asynchronous data buffer having buffer write and read pointers 1 2006
7,805,586 System and method for optimizing interconnections of memory devices in a multichip module 2 2006
7,596,641 System and method for transmitting data packets in a computer system having a memory hub architecture 1 2006
7,489,875 System and method for multiple bit optical data transmission in memory systems 1 2006
7,434,081 System and method for read synchronization of memory modules 1 2006
7,266,633 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 8 2006
7,529,273 Method and system for synchronizing communications links in a hub-based memory system 3 2006
7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 5 2006
7,411,807 System and method for optically interconnecting memory devices 2 2006
7,382,639 System and method for optically interconnecting memory devices 1 2006
7,412,571 Memory arbitration system and method having an arbitration packet protocol 7 2007
7,646,655 Memory device with fail search and redundancy 2 2007
7,823,024 Memory hub tester interface and method for use thereof 1 2007
7,774,559 Method and system for terminating write commands in a hub-based memory system 9 2007
7,596,675 Memory hub architecture having programmable lane widths 3 2008
8,082,404 Memory arbitration system and method having an arbitration packet protocol 0 2008
8,392,686 System and method for read synchronization of memory modules 0 2008
8,412,987 Non-volatile memory to store memory remap information 0 2009
8,412,985 Hardwired remapped memory 0 2009
8,015,384 Memory hub architecture having programmable lane widths 0 2009
7,949,803 System and method for transmitting data packets in a computer system having a memory hub architecture 0 2009
8,239,607 System and method for an asynchronous data buffer having buffer write and read pointers 0 2009
8,291,173 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 0 2010
8,190,819 System and method for optimizing interconnections of memory devices in a multichip module 0 2010
8,438,329 System and method for optimizing interconnections of components in a multichip memory module 0 2011
8,346,998 System and method for transmitting data packets in a computer system having a memory hub architecture 0 2011
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (13)
6,442,085 Self-Test pattern to detect stuck open faults 5 2000
7,085,971 ECC based system and method for repairing failed memory elements 6 2001
6,768,694 Method of electrically blowing fuses under control of an on-chip tester interface apparatus 31 2002
6,856,569 Method and system for merging multiple fuse decompression serial bitstreams to support auxiliary fuseblow capability 12 2003
7,210,085 Method and apparatus for test and repair of marginally functional SRAM cells 1 2003
8,245,105 Cascade interconnect memory system with enhanced reliability 0 2008
8,234,540 Error correcting code protected quasi-static bit communication on a high-speed bus 0 2008
8,201,069 Cyclical redundancy code for use in a high-speed serial link 0 2008
8,139,430 Power-on initialization and test for a cascade interconnect memory system 1 2008
8,082,474 Bit shadowing in a memory system 0 2008
8,082,475 Enhanced microprocessor interconnect with bit shadowing 0 2008
7,895,374 Dynamic segment sparing and repair in a memory system 1 2008
7,979,759 Test and bring-up of an enhanced cascade interconnect memory system 0 2009
 
LSI LOGIC CORPORATION (12)
6,367,042 Testing methodology for embedded memories using built-in self repair and identification circuitry 73 1998
6,496,950 Testing content addressable static memories 11 1999
6,496,947 Built-in self repair circuit with pause for data retention coverage 31 1999
6,634,003 Decoding circuit for memories with redundancy 8 2000
6,651,202 Built-in self repair circuitry utilizing permanent record of defects 76 2001
6,567,325 Apparatus and method for system access to tap controlled BIST of random access memory 6 2001
6,928,598 Scan method for built-in-self-repair (BISR) 4 2001
7,260,758 Method and system for performing built-in self-test routines using an accumulator to store fault information 18 2001
7,076,699 Method for testing semiconductor devices having built-in self repair (BISR) memory 9 2001
7,007,201 Shared embedded trace macrocell 16 2001
6,871,297 Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories 13 2002
7,017,093 Circuit and/or method for automated use of unallocated resources for a trace buffer application 7 2002
 
SUN MICROSYSTEMS, INC. (9)
6,769,081 Reconfigurable built-in self-test engine for testing a reconfigurable memory 68 2000
7,096,393 Built-in self-test (BIST) of memory interconnect 4 2002
7,020,820 Instruction-based built-in self-test (BIST) of external memory 4 2002
7,062,694 Concurrently programmable dynamic memory built-in self-test (BIST) 7 2003
7,127,640 On-chip testing of embedded memories using Address Space Identifier bus in SPARC architectures 0 2003
7,260,759 Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors 4 2004
7,178,076 Architecture of an efficient at-speed programmable memory built-in self test 13 2004
7,293,199 Method and apparatus for testing memories with different read/write protocols using the same programmable memory bist controller 0 2004
7,206,979 Method and apparatus for at-speed diagnostics of embedded memories 9 2004
 
NVIDIA CORPORATION (7)
6,288,418 Multiuse input/output connector arrangement for graphics accelerator integrated circuit 28 1999
7,404,171 System and method for configuring semiconductor functional circuits 0 2003
8,021,193 Controlled impedance display adapter 0 2005
7,793,029 Translation device apparatus for configuring printed circuit board connectors 4 2005
8,417,838 System and method for configurable digital communication 0 2005
8,412,872 Configurable GPU and method for graphics processing using a configurable GPU 0 2005
8,021,194 Controlled impedance display adapter 0 2007
 
NETLOGIC MICROSYSTEMS, INC. (6)
7,237,156 Content addressable memory with error detection 7 2001
7,043,673 Content addressable memory with priority-biased error detection sequencing 9 2001
6,978,343 Error-correcting content addressable memory 14 2002
7,257,763 Content addressable memory with error signaling 12 2003
7,304,873 Method for on-the-fly error correction in a content addressable memory (CAM) and device therefor 5 2005
7,283,380 Content addressable memory with selective error logging 11 2005
 
SYNOPSYS, INC. (5)
7,127,647 Apparatus, method, and system to allocate redundant components 12 2001
7,237,154 Apparatus and method to generate a repair signature 11 2002
7,149,924 Apparatus, method, and system having a pin to activate the self-test and repair instructions 12 2002
7,149,921 Apparatus, method, and system to allocate redundant components with subsets of the redundant components 10 2002
7,290,186 Method and apparatus for a command based bist for testing memories 7 2003
 
KABUSHIKI KAISHA TOSHIBA (4)
6,246,617 Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device 14 2000
6,718,496 Self-repairing semiconductor device having a testing unit for testing under various operating conditions 16 2000
7,414,905 Semiconductor integrated circuit and testing method therefor 0 2007
7,653,854 Semiconductor integrated circuit having a (BIST) built-in self test circuit for fault diagnosing operation of a memory 8 2007
 
MARVELL INTERNATIONAL TECHNOLOGY LTD. (4)
7,418,642 Built-in-self-test using embedded memory and processor in an application specific integrated circuit 6 2001
7,890,828 Built-in self-test using embedded memory and processor in an application specific integrated circuit 3 2008
8,046,652 Built-in self-test using embedded memory and processor in an application specific integrated circuit 1 2011
8,321,731 Built-in-self-test using embedded memory and processor in an application specific integrated circuit 2011
 
ADVANTEST (SINGAPORE) PTE LTD (3)
7,076,714 Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors 6 2003
7,743,304 Test system and method for testing electronic devices using a pipelined testing architecture 4 2006
8,347,156 Test system and method for testing electronic devices using a pipelined testing architecture 0 2010
 
GOOGLE INC. (3)
6,643,807 Array-built-in-self-test (ABIST) for efficient, fast, bitmapping of large embedded arrays in manufacturing test 36 2000
6,625,769 Method for IC fault analysis using programmable built-in self test and optical emission 13 2000
7,222,274 Testing and repair methodology for memories having redundancy 9 2004
 
SAMSUNG ELECTRONICS CO., LTD. (3)
7,539,598 Semiconductor test apparatus and method thereof and multiplexer and method thereof 1 2004
7,692,995 Redundancy program circuit and methods thereof 0 2008
7,606,090 Redundancy program circuit and methods thereof 0 2008
 
AVAGO TECHNOLOGIES GENERAL IP PTE. LTD. (2)
6,914,833 Apparatus for random access memory array self-repair 3 2003
7,519,875 Method and apparatus for enabling a user to determine whether a defective location in a memory device has been remapped to a redundant memory portion 2 2005
 
CREDENCE SYSTEMS CORPORATION (2)
6,304,989 Built-in spare row and column replacement analysis system for embedded memories 39 1999
6,587,979 Partitionable embedded circuit test system for integrated circuit 50 2000
 
CYPRESS SEMICONDUCTOR CORPORATION (2)
6,675,336 Distributed test architecture for multiport RAMs or other circuitry 6 2000
8,073,005 Method and apparatus for configuring signal lines according to idle codes 0 2007
 
FARADAY TECHNOLOGY CORP. (2)
6,459,638 Built-in programmable self-diagnostic circuit for SRAM unit 2 2001
6,529,430 Built-in programmable self-diagnostic circuit for SRAM unit 2 2002
 
INTEL CORPORATION (2)
6,671,837 Device and method to test on-chip memory in a production environment 5 2000
6,795,948 Weighted random pattern test using pre-stored weights 4 2000
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (2)
7,372,251 Semiconductor integrated circuit and memory test method 1 2005
7,295,028 Semiconductor integrated circuit and memory test method 0 2005
 
PANASONIC CORPORATION (2)
6,917,215 Semiconductor integrated circuit and memory test method 10 2003
7,739,563 Semiconductor integrated circuit and memory test method 0 2008
 
PITNEY BOWES INC. (2)
8,060,453 System and method for funds recovery from an integrated postal security device 1 2008
8,055,936 System and method for data recovery in a disabled integrated circuit 0 2008
 
QIMONDA AG (2)
6,590,816 Integrated memory and method for testing and repairing the integrated memory 129 2002
7,356,741 Modular test controller with BIST circuit for testing embedded DRAM circuits 1 2002
 
ADVANCED MICRO DEVICES, INC. (1)
6,560,740 Apparatus and method for programmable built-in self-test and self-repair of embedded memory 66 1999
 
ADVANTEST CORPORATION (1)
6,885,956 Semiconductor test apparatus 4 2003
 
ARM LIMITED (1)
7,434,119 Method and apparatus for memory self testing 1 2005
 
ARM, INC. (1)
6,973,605 System and method for assured built in self repair of memories 14 2002
 
GIGA SEMICONDUCTOR, INC. (1)
6,775,193 System and method for testing multiple embedded memories 0 2003
 
GRUNDFOS MANAGEMENT A/S (1)
8,315,115 Method for testing a main memory 0 2008
 
HYNIX SEMICONDUCTOR INC. (1)
7,421,636 Semiconductor memory device having a test control circuit 4 2005
 
INFINEON TECHNOLOGIES AG (1)
7,424,657 Method and device for testing an integrated circuit, integrated circuit to be tested, and wafer with a large number of integrated circuits to be tested 0 2001
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
7,536,614 Built-in-redundancy analysis using RAM 0 2006
 
JONES FARM TECHNOLOGY, LLC (1)
6,697,978 Method for testing of known good die 4 2000
 
LG ELECTRONICS INC. (1)
6,675,329 Internal memory in application specific integrated circuit device and method for testing internal memory 7 2000
 
MELLANOX TECHNOLOGIES LTD. (1)
6,667,918 Self-repair of embedded memory arrays 15 2002
 
MENTOR GRAPHICS CORPORATION (1)
6,421,794 Method and apparatus for diagnosing memory using self-testing circuits 29 2000
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
6,504,772 Testing method and test apparatus in semiconductor apparatus 7 2001
 
NEC CORPORATION (1)
6,854,081 Initializing/diagnosing system in on-chip multiprocessor system 3 1999
 
NZ APPLIED TECHNOLOGIES CORPORATION (1)
6,571,364 Semiconductor integrated circuit device with fault analysis function 3 1999
 
SANDISK TECHNOLOGIES INC. (1)
7,962,682 Multi-module simultaneous program, erase test, and performance method for flash memory 0 2006
 
SILICON STORAGE TECHNOLOGY, INC. (1)
6,788,595 Embedded recall apparatus and method in nonvolatile memory 7 2002
 
STMICROELECTRONICS S.R.L. (1)
7,213,185 Built-in self test circuit for integrated circuits 8 2003
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
6,930,934 High efficiency redundancy architecture in SRAM compiler 1 2003
 
TEXAS INSTRUMENTS INCORPORATED (1)
6,952,623 Permanent chip ID using FeRAM 5 2002
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
7,162,660 Semiconductor memory and method of testing the same 6 2003