Reconfigurable processor for executing successive function sequences in a processor operation
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United States of America Patent
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May 23, 2000
Issued Date -
N/A
app pub date -
Nov 9, 1995
filing date -
Nov 30, 1993
priority date (Note) -
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Abstract
A digital processor with reconfigurable architecture includes a processor input and a processor output. A library stores a plurality of related function sequences for executing a processor operation. Memory stores data as required by the function sequences. A configurable device is connected to the library and the memory and between the processor input and the processor output. The configurable device sequentially stores the function sequences from the library in a plurality of programmable gate arrays configurable by the function sequences. The configurable device reconfigures the programmable gate arrays with another of the function sequences to complete the processor operation.
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