Adjustable output driver circuit having parallel pull-up and pull-down elements
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United States of America Patent
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-
May 30, 2000
Issued Date -
N/A
app pub date -
Sep 3, 1998
filing date -
Jan 6, 1997
priority date (Note) -
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Abstract
An output driver circuit offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry is described for improving high frequency operation.
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