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Abstract

A digital delay lock loop (DLL) circuit for clock signals with reduced delay line length includes a first phase difference detector for detecting a first phase difference, and a second phase difference detector for detecting a second phase difference. The circuit further includes an inverter for inverting an input clock signal, and a switch controlled by the second phase difference detector for switching between the input clock signal and the inverted input clock signal in accordance with the second phase difference to provide a clock signal to the first phase difference detector. In a method aspect, a method for reducing delay line length in a digital delay locked loop (DLL) includes determining a phase difference between an input clock signal and a feedback clock signal, and maintaining the phase difference between the input clock signal and the feedback clock signal within approximately 180.degree.. The method also includes delaying the input clock signal to compensate for the phase difference, wherein a number of delay cells utilized is reduced by approximately one-half.

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First Claim