Method and apparatus for congestion driven placement
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
May 30, 2000
Grant Date -
N/A
app pub date -
Aug 6, 1997
filing date -
Aug 6, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that wire routine be done correctly to avoid any congestion of wires. Placement of the cells and the routing of the wires to avoid congestion can be accomplished by determining congestion of various regions of the IC's after an initial placement of the cells and routing of the wires. The present invention discloses a method and apparatus to determine the congestion of the regions and a technique to increase the fictive heights (or, the 'working height', or the 'working size') of the cells for repeating the placement of the cells if the current placement and routing leads to congestion. The present invention provides for a method of defining regions and line segment. Then, each segment is analyzed to determine the ratio of the wire density of the segment to the wire capacity of the segment. If the ratio is greater than a predetermined value, then the fictive heights of the cells of the affected regions are increased and the placement is repeated.
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