Cache memory cell with a pre-programmed state
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United States of America Patent
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May 30, 2000
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N/A
app pub date -
Dec 2, 1997
filing date -
Dec 2, 1997
priority date (Note) -
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Abstract
A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data written into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.
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