Importance

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Abstract

A circuit and method for performing a delay locked function for correcting phase differences between an input clock signal RCLK and an internally generated clock signal ICLK and for controlling the correcting step to maintain an accurate locking operation when a phase difference is below a threshold valve (the maximum time for which the internal step jitter may occur). The circuit includes an earlier state detection unit for delaying an input clock signal RCLK for a predetermined time and comparing a phase of an input clock signal RCLK with a phase of an internal clock signal ICLK, a later state detection unit for delaying the internal clock signal ICLK for a predetermined time and comparing a phase of the internal clock signal ICLK with the phase of the input clock signal RCLK, a delay controller for outputting a control signal for determining a delay time of the input clock signal RCLK in accordance with a comparison result by the earlier state detection unit and the later state detection unit, and a variable delay unit for delaying the input clock signal for a predetermined time in accordance with a control signal from the delay controller and outputting an internal clock signal ICLK.

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First Claim