Device for rapid simulation of logic circuits
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United States of America Patent
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Jun 6, 2000
Grant Date -
N/A
app pub date -
Feb 2, 1998
filing date -
Oct 22, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A logical simulation device has a delay value calculations section to calculate delay values of circuit blocks in a semiconductor integrated circuit as a target of logical simulation based on logical circuit information relating to the logical circuit blocks, input test patterns as operational descriptions of used in circuit verification, and delay value calculation information stored in a delay value and timing check value calculation library, and a logical simulation section performs the logical simulation of the semiconductor integrated circuit based on the calculated delay values.
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