Skewing-suppressive output buffer circuit
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United States of America Patent
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-
Jun 6, 2000
Grant Date -
N/A
app pub date -
Jan 21, 1999
filing date -
Jan 22, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
In an output buffer circuit, an input signal is transmitted through a bus by way of a latch circuit and a driver. A stable-state interval detector detects an interval during which the input signal remains in the same logical state. If the stable-state interval detected is relatively short, a drivability controller controls the drivability of the driver at a normal value. To the contrary, if the interval detected is relatively long, the controller increases the drivability of the driver. In general, if the stable-state interval of an input signal is relatively long, then the time taken for the subsequent logical state transition of the signal tends to be longer as compared with a signal having a shorter stable-state interval. However, if the drivability of the driver is increased, then the state transition time is shortened, and substantially equalized with that of a signal having a relatively short stable-state interval. As a result, signal skewing can be minimized.
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