Semiconductor device having a multi-layer metal interconnect structure
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United States of America Patent
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Jun 13, 2000
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N/A
app pub date -
Mar 5, 1999
filing date -
Mar 5, 1999
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Abstract
A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.
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