High performance cost optimized memory with delayed memory writes
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United States of America Patent
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Jun 13, 2000
Grant Date -
N/A
app pub date -
Oct 9, 1998
filing date -
Oct 10, 1997
priority date (Note) -
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Abstract
A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.
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