Multimedia computer architecture with multi-channel concurrent memory access
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United States of America Patent
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Jun 13, 2000
Issued Date -
N/A
app pub date -
Sep 30, 1997
filing date -
Dec 31, 1996
priority date (Note) -
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Abstract
A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to memory. Arbitration and snoop logic controls access to each memory channel and maintains cache coherency. A host CPU, multimedia processor, pipes processor and display controller may independently and concurrently access memory. The pipes processor provides a decoupled input/output processor for universal serial bus and firewire serial buses to free up the host CPU.
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