Programmable logic device using a two bit security scheme to prevent unauthorized access
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United States of America Patent
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Jun 13, 2000
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N/A
app pub date -
Jan 20, 1998
filing date -
Feb 14, 1997
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Abstract
For a data processing device having a main memory comprised of a non-volatile memory and a CPU, memory protection and security are ensured for its programs and so forth. An auxiliary memory for storing security bit data is provided, for example, in an EPROM that comprises the main memory. Assuming that the result read by the CPU is '0' when a current flows between a drain and a source of a transistor in the EPROM, and '1' when the current does not flow, then the security bit data read from two transistors A and B are A=1 and B=1, which means they are set so that access to the main memory and a write to the auxiliary memory are prohibited. With A=0 and B=0, security is set, but a write to the auxiliary memory is permitted; with A=1 (0) and B=0 (1), security is reset.
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