Memory array having a multi-state element and method for forming such array or cellis thereof
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United States of America Patent
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Jun 20, 2000
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N/A
app pub date -
Feb 5, 1999
filing date -
Jun 7, 1995
priority date (Note) -
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Abstract
A memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have active areas formed above the electrodes, and a conductive layer electrically coupling at least a portion of the active areas. The memory array can also include a dielectric volume surrounding at least a portion of the plurality of electrodes. The electrodes can be contacts, plugs or pillars deposited in etched openings in the dielectric volume.
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