Method for forming a DRAM having improved capacitor dielectric layers
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United States of America Patent
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Jun 20, 2000
Grant Date -
N/A
app pub date -
Jun 2, 1998
filing date -
Jun 2, 1998
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Abstract
A method of fabricating a DRAM device having nitride/oxide or tantalum pentoxide dielectric layers. The method includes: forming field oxide regions on a substrate to define active regions; forming at each active region a MOSFET comprising a top dielectric layer; forming a contact window in the MOSFET top dielectric layer; generating a doped poly-Si bottom electrode of a capacitor in electrical connection with the MOSFET through the contact window; removing surface oxide of the bottom electrode using both chemical and inductive coupled plasma (ICP) treatments; depositing nitride/oxide dielectric layers or a tantalum pentoxide dielectric layer on the ICP-treated bottom electrode; generating a doped poly-Si top electrode of the capacitor.
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