Synchronous semiconductor memory device with double data rate scheme
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United States of America Patent
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Jun 20, 2000
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N/A
app pub date -
Mar 18, 1998
filing date -
Mar 18, 1997
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Abstract
Disclosed is a synchronous semiconductor device having a double data rate input circuit which allows data to be written in the device in response to a clock signal and a data strobe signal. The input circuit stores a pair of data which is synchronized with either the clock signal or the data strobe signal, thereby processing data at high speed. In case the data strobe is used, data setup and hold window margin is improved.
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